This invention relates to a circuit arrangement for measuring leakage current, particularly in a semiconductor integrated circuit tester.
It is necessary to be able to measure low currents in the parametric testing of a semiconductor integrated circuit device. For example, the input leakage test on a pin of a device under test (DUT) fabricated with CMOS technology may be less than 100 pA. In order to measure the input leakage current, all sources of parasitic leakage are disconnected from the pin and the specified voltage at which the current is to be measured is forced on the pin and the resulting current flow is measured using a parametric measurement unit (PMU). Currently the input voltages may be in the range from -2 volts to +15 volts. The current flow can be monitored by observing the voltage drop in a series pass impedance, such as a resistor or a capacitor. When the series pass impedance is a capacitor, the voltage drop across the capacitor represents the integral of the current flow through the capacitor. By adjusting the integration interval to be a fixed and precise duration, the sensitivity of the voltage drop to current flow is constant. This is expressed by the relation: EQU E.sub.cap =(I*.increment.T)/C
where C is the capacitor value, I is the current to be measured and .increment.T is the duration of the integration interval. Prior to the beginning of the integration interval, the voltage E.sub.cap across the capacitor is typically reduced to zero by closing a FET switch. At the beginning of the integration interval, the FET switch is opened. The voltage is measured at the end of the integration interval. A FET switch is employed because mechanical relays are too slow to allow short integration intervals and short intervals between integrations.